Error (10170): Verilog HDL syntax error at dada.v(21) near text "if"; expecting "endmodule"

module dada(CLK,light_state,E_R,E_G,E_Y,W_R,W_G,W_Y,S_R,S_G,S_Y,N_R,N_G,N_Y,contro11,control2,dout);
input CLK;
input contro11,control2;
output E_R,E_G,E_Y,W_R,W_G,W_Y,S_R,S_G,S_Y,N_R,N_G,N_Y;
output [2:0]light_state;
output [6:0]dout;
reg E_R,E_G,E_Y,W_R,W_G,W_Y,S_R,S_G,S_Y,N_R,N_G,N_Y;
reg [8:0] count1;
reg [4:0]count2;
reg [1:0] count3;
reg [6:0] dout;
parameter ST0=0,ST1=1,ST2=2,ST3=3,ST4=4;
parameter num1=7'b0110000,num2=7'b1101101,num3=7'b1111001,num4=7'b0110011,num5=7'b1011011,num6=7'b1011111,num7=7'b1110000,num8=7'b1111111,num9=7'b1111011;
reg[2:0] light_state;
always@(negedge CLK )
if(count1<12)
count1 <= count1 + 1;
else
count1<=0;
if(count1/2==0)
dout<=num9;
if(count1/2==1)
dout<=num8;
else if(count1/2==2)
dout<=num7;
else if(count1/2==3)
dout<=num6;
else if(count1/2==4)
dout<=num5;
else if(count1/2==5)
dout<=num4;
else
dout<=num8;
always@(negedge CLK )
if(count2<6)
count2 <= count2 + 1;
else
count2<=0;
if(count2/2==0)
dout<=num3;
else if(count2/2==1)
dout<=num2;
else if(count2/2==2)
dout<=num1;
else
dout<=num8;
always@(negedge CLK )
if(count3<1)
count3 <= count3 + 1;
else
count3<=0;
always@(negedge CLK)

---

always内部出现多个if时，需要begin end来包住。另外，模块结尾需要endmodule

---

endmodule,,你没写
always @（***）
begin
if**********
**
***
end
你那备旁森种方式已经不符仿亩合启神逻辑了。

---