Error (10170): Verilog HDL syntax error at aa1.v(1) near text ";"; expecting ".", or an identifier

程序如下：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
input clk;
output cb_out;
reg cb_out;

entity ss is
port (cb_out: in std_logic_vector(6 downto 0);
clk:in std_logic;
ss: out std_logic_vector(2 downto 0));
end ss;

architecture myarch of ss is
begin
process(clk,cb_out)
begin
if rising_edge(clk) then
ss(2)<=cb_out(6) xor cb_out(5) xor cb_out(4) xor cb_out(2);
ss(1)<=cb_out(6) xor cb_out(5) xor cb_out(3) xor cb_out(1);
ss(0)<=cb_out(6) xor cb_out(4) xor cb_out(3) xor cb_out(0);
end if;
end process;
end myarch;

系统总是提示
Error (10170): Verilog HDL syntax error at aa1.v(1) near text ";"; expecting ".", or an identifier
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 1 error, 8 warnings
Error: Peak virtual memory: 271 megabytes
Error: Processing ended: Fri Jun 03 11:38:54 2016
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 3 errors, 0 warnings

求助！！！！

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