Error (10170): Verilog HDL syntax error at test.v(1) near text '

源程序是

'include "cpu.v"
module top
endmodule

这不是很简单的程序么，工程里也包含了CPU.V文件，为什么会有问题？
Error (10170): Verilog HDL syntax error at test.v(1) near text '
Error (10170): Verilog HDL syntax error at test.v(1) near text "'"; expecting an identifier, or "module", or "macromodule", or "function", or "parameter", or "primitive", or "real", or "realtime", or "reg", or "specparam", or "task", or "time", or "integer", or "config", or "localparam", or "(*", or "include", or "library"

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include应该用的胡亮是`而不是'
`include "cpu.v"
`是在键盘数字1左边那并衫个符号,不绝做腔是引号.

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同意楼上的，我刚开始学的时候也把那个符号搞错了

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