Xilinx+Modelsim仿真，在ISE用VHDL写了test_bench，可是进入Modelsim后输入信号都是零，怎么办？

test_bench:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY Phy_buffer_test_tb_0 IS
END Phy_buffer_test_tb_0;

ARCHITECTURE testbench_arch OF Phy_buffer_test_tb_0 IS
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
COMPONENT Phy_buffer
PORT (
clk : In std_logic;
reset : In std_logic;
ant_info : In std_logic;
vld : In std_logic;
din : In std_logic_vector (31 DownTo 0);
finish : Out std_logic;
dout : Out std_logic_vector (31 DownTo 0);
vld_hold : Out std_logic
);
END COMPONENT;
SIGNAL clk : std_logic := '0';
SIGNAL reset : std_logic := '0';
SIGNAL ant_info : std_logic := '0';
SIGNAL vld : std_logic := '0';
SIGNAL din : std_logic_vector (31 DownTo 0) := "00000000000000000000000000000000";
SIGNAL finish : std_logic := '0';
SIGNAL dout : std_logic_vector (31 DownTo 0) := "00000000000000000000000000000000";
SIGNAL vld_hold : std_logic := '0';
constant PERIOD : time := 200 ns;
constant OFFSET : time := 100 ns;

BEGIN
UUT : Phy_buffer
PORT MAP (
clk => clk,
reset => reset,
ant_info => ant_info,
vld => vld,
din => din,
finish => finish,
dout => dout,
vld_hold => vld_hold
);
clk_1:PROCESS -- clock process for clk
BEGIN
WAIT for OFFSET;
CLOCK_LOOP : LOOP
clk <= '0';
WAIT FOR PERIOD/2 ;
clk <= '1';
WAIT FOR PERIOD/2;
END LOOP CLOCK_LOOP;
END PROCESS;
reset_1:PROCESS
BEGIN
WAIT FOR 320 ns;
reset <= '1';
WAIT FOR 133 ns;
reset <= '0';
END PROCESS;
data_1:process
begin
if reset = '1' then
din <=(others =>'0');
elsif rising_edge(clk) then
din<=din+1;
end if;
end process;
ant_info_1:PROCESS
BEGIN
ant_info <= '0';
END PROCESS;

vld_1:process
begin
wait for 500 ns;
VLD_LOOP : LOOP
vld <= '1';
WAIT FOR PERIOD * 120;
vld <= '0';
WAIT FOR PERIOD * 340;
END LOOP VLD_LOOP;
end process;
END testbench_arch;

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clock 别用loop

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