Error (10170): Verilog HDL syntax error at smg.v(9) near text "if"; expecting "endmodule"

简单的数码管。。。呃,错误在题目上 代码在下面 谢谢
module smg(HEX0,CLOCK_27,TD_RESET);
output HEX0;
input TD_RESET;
input CLOCK_27;
reg[27:0] cnt;
reg[7:0] HEX01;
reg[3:0] smg_zhi;
always @ (posedge CLOCK_27 or negedge TD_RESET);
if(!TD_RESET)begin
cnt<=27'd0;smg_zhi<=4'b1;
end
else if (cnt == 27'd27000000)
begin
cnt <= 27'd0;
if (smg_zhi==4'd9)
smg_zhi=4'd0;
else smg_zhi=smg_zhi+1'b1;

end
else
cnt <= cnt+1'b1;

always @ (smg_zhi)
case (smg_zhi)
4'b0001:HEX01=7'd192;
4'b0001:HEX01=7'd249;
4'b0001:HEX01=7'd164;
4'b0001:HEX01=7'd176;
4'b0001:HEX01=7'd153;
4'b0001:HEX01=7'd146;
4'b0001:HEX01=7'd130;
4'b0001:HEX01=7'd1248;
4'b0001:HEX01=7'd128;
4'b0001:HEX01=7'd144;

endcase
assign HEX0=HEX01;
endmodule
第九行always块括号后面多了“;”